The present invention relates generally to an over-current protection circuit of a constant voltage circuit. The present invention also relates to an over-current protection circuit having an output characteristic that resembles a stair shape. Moreover, the present invention relates to an electric apparatus that includes an over-current protection circuit.
FIG. 7 of Japanese Patent No. 3782726 (Japanese Patent Publication No. 2003-186554) shows an over-current protection circuit of a constant voltage circuit shown in FIG. 8. FIG. 9 of Japanese Patent No. 3782726 is a chart that illustrates output characteristics of the circuit of FIG. 8. The output characteristic chart of FIG. 9 indicates a relationship between an output voltage Vout and an output current lout of the circuit of FIG. 8.
FIGS. 8 and 9 of Japanese Patent No. 3782726 correspond to a conventional over-current protection circuit. In FIG. 8, a reference voltage Vref and a divided voltage are provided as inputs to an error amplifier (AMP). The divided voltage is provided by dividing the output voltage Vout using resistors R13 and R14.
The error amplifier (AMP) amplifies a difference between the reference voltage Vref and the divided voltage to provide a control signal that controls an output control transistor M16. A gate of the output control transistor M16 receives the control signal, so that the output voltage Vout at a drain of the output control transistor M16 is controlled to a predetermined voltage value.
The output transistor M16 and a current detecting transistor M11 are P-channel type MOS (PMOS) transistors, having respective sources that are connected to each other and respective gates that are connected to each other. A drain current Id11 of the current detecting transistor M11 is proportional to a drain current of the output control transistor M16.
The drain current Id11 is separated into three paths. One of three paths includes a resistance R15 and an N-channel MOS (NMOS) transistor M17, the second of three paths includes a resistance R11 and an NMOS transistor M12, and the third of three paths includes an NMOS transistor M14.
The output voltage Vout is divided to provide a divided voltage to the gates of NMOS transistor M17 and NMOS transistor M12. A voltage that is used to power the over-current protection circuit is referred to as a rating voltage. When the output voltage Vout is equal to the rating voltage, the divided voltages provided to the gates of the respective NMOS transistors M17 and M12 are greater than the respective threshold voltages of NMOS transistors M17 and M12, thereby turning on NMOS transistors M17 and M12.
NMOS transistors M15 and M14 form a current mirror circuit. A drain current of the NMOS transistor M15 is proportional to a drain current of the NMOS transistor M14. The drain current of the NMOS transistor M15 connects to a resistance R12 serially. Accordingly, a voltage drop occurs across the resistance R12 to provide an electric potential at a gate of a PMOS transistor M13. A drain of the PMOS transistor M13 is connected to the gate of output control transistor M16.
A conventional technique for generating an output characteristic that resembles a stair shape will now be described. When an output current of the constant voltage circuit shown in FIG. 8 of Japanese Patent No. 3782726 rises (cf. reference “a”) until it reaches a limit current 1 (cf. FIG. 9), a value of the voltage provided by resistance R12 decreases to the threshold voltage of the PMOS transistor M13, and the PMOS transistor M13 is turned off. At that time, a gate voltage potential of the output control transistor M16 is inhibited from decreasing, and the output current lout is inhibited from increasing. Thus, the output voltage Vout decreases to correspond to a limit current 1 value (cf. (b)).
When the output voltage Vout decreases, the gate voltage potential of the NMOS transistors M17 and M12 decreases. First, when the gate voltage potential of the NMOS transistor M17 that is smaller than the divided voltage of the output voltage Vout decreases to a value less than the threshold potential, the NMOS transistor M17 turns off. When the NMOS transistor M17 turns off, a part of the drain current of the current detecting transistor M11 that flowed through the resistance R15 and the NMOS transistor M17 does not flow. Rather, this part of the drain current is added to the drain current of the NMOS transistor M14.
As a result, since the voltage drop across the resistance R12 increases, the gate potential of the PMOS transistor M13 decreases more. Thus, an on-state resistance value of the PMOS transistor M13 decreases, and the gate potential of the output control transistor M16 is pulled up more. Therefore, the output current lout decreases to a limit current 2 of FIG. 9 (cf. (c)).
Furthermore, when the output Vout decreases, the NMOS transistor M12 is turned off, and a part of the drain current of the current detecting transistor M11 that flowed through the resistance R11 and the NMOS transistor M12 does not flow. Rather, this part of the drain current is added to the drain current of NMOS transistor M14.
As a result, since the voltage drop across the resistance R12 increases, the voltage potential at an output of the resistance R12 decreases more. Since the gate potential of the PMOS transistor M13 decreases further, the gate potential of the output control transistor M16 is pulled up more. Thus, the output current Iout decreases to a limit current 3 of FIG. 9 (cf. e).
As described above, the output current Iout of the constant voltage circuit shown in FIG. 8 of Japanese Patent No. 3782726 can decrease in a manner that resembles a stair shape corresponding with the decreasing output voltage Vout.
Japanese Patent Application No. 2004-233619 describes similar conventional art.